Modern semiconductor based integrated circuits (ICs) are incredibly complex and contain millions of circuit devices, such as transistors, and millions of interconnections between the circuit devices. Designing such complex circuits cannot be accomplished manually, and circuit designers use computer based Electronic Design Automation (EDA) tools for schematics, layouts, simulation, and verification of the complex circuits. Furthermore, EDA tools allow circuit designers to optimize a complex electronic circuit, for example, by reducing the footprints of the various circuit devices.
EDA tools typically use design rule checking (DRC) to determine whether the physical layout of a particular chip layout satisfies a series of recommended parameters called design rules. Design rules are specific to a particular semiconductor manufacturing process. A design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor processes, so as to ensure that most of the parts work correctly. For example, a maximum resistance constraint between two circuit devices is a common design rule.
Conventional methods for checking if the maximum resistance constraint is violated are not efficient. Typically, the conventional methods may first do a complete routing of the net between the two circuit devices then run a checker that will compute the total resistance of each wire segment in the net. If the resistance does not satisfy the maximum resistance constraint, the circuit designer may change the resistance of one or more wire segments. For example, the width of one or more wire segments in the net may be changed. Alternatively, the wire segments may be rerouted. Then the checker may compute the new resistance of the wires segments and run the design rule checking again. This loop may be repeated while the resistance of the net does not satisfy the maximum resistance constraint. This loop is either done manually by a user or automatically by a router. In either case, the entire net has to be fully routed before the design rule checking. The conventional methods are therefore tedious. They take time, require many iterations and many routing modification to make the design satisfy the maximum resistance constraint, especially when the user or circuit designer creates the net manually.
It is desired to have EDA tools that solve the aforementioned problems of excess complexity and inefficiency. It is desired to have EDA tools that can estimate a wire resistance that satisfies the maximum resistance constraint, render the resistance dynamically and/or automatically update the wire segments width accordingly while the user is editing wire segments without having to route the entire net, so that the user or the EDA tool can adjust the resistance in the partially routed net to converge faster to a final design that has no resistance violation.